This invention relates generally to CMOS semiconductor transistors and circuits, and more particularly the invention relates to CMOS transistors having dual work function metal gates and methods of manufacturing the same.
In producing high performance bulk CMOS integrated circuits, both n-MOS and p-MOS transistors must have low threshold voltages (VT). This in turn requires that the gate electrodes for the n-MOS and p-MOS transistors have different work functions. The desired work function for n-MOS transistors is around 4.1 V and the desired work function for p-MOS transistors is around 5.2 V.
Polycrystalline silicon has remained the gate electrode material of choice for many years. The work function of the polycrystalline silicon can be varied from approximately 4.1 to 5.2 V by implanting either donor (n) or acceptor (p) atoms respectively. As device scaling continues beyond the 100 nm technology node, polycrystalline silicon might no longer remain the best choice for this application. The resistance of the polycrystalline silicon gate electrode is limited by the electrically active dopant concentration that can be obtained in the gate. Metal gate electrodes overcome these limitations, due to high free electron concentration in the metallic materials. Polycrystalline silicon is also unstable on the many advanced (high permittivity) gate dielectrics.
Further, as the channeling of CMOS transistors continues to be scaled beyond 100 nm, the capacitance equivalent thickness (CET) of the gate dielectric has to be reduced to less than 15 xc3x85. One way to decrease the CET while maintaining acceptable gate leakage is to use high-k dielectrics instead of silicon oxide. Another way is to replace the polysilicon gate with a metal gate, as noted above, thus eliminating depletion at the gate/dielectric interface and reducing the CET by a couple of angstroms. In addition, metal gate materials may ultimately be necessary for high-k gate dielectrics because polycrystalline silicon has been found to be thermodynamically unstable on some high-k materials such as Ta2O5 and ZrO2 In order to achieve surface-channel p- and n-MOSFETs with low and symmetrical threshold voltages, two different metals with different work functions must be used in a metal gate CMOS technology. A straightforward process for dual-metal gate technology includes blanket deposition of a first gate metal followed by selectively removing the first metal from either the n-MOS or p-MOS regions. Thereafter, a second gate metal is deposited over the entire wafer. Afterwards, the n-MOS and p-MOS gate electrodes are patterned. Unfortunately, this approach exposes the gate dielectric to a metal-etching process in the regions from which the first gate metal is selectively removed, and consequently causes undesirable thinning of the gate dielectric and potential reliability problems.
The present invention is directed to an improved method of fabricating dual metal gates for CMOS transistors and the resulting structures.
Briefly, the interdiffusion of metals is employed to form dual metal gates with different work functions without the need for removing metal from the gate dielectric.
In one embodiment, two layers of different metals are formed on gate dielectric overlying P and N wells in a semiconductor substrate. The top or second layer of metal is removed from over one well, and then the metal layers are annealed at an elevated temperature. The bottom or first layer of metal forms a first metal gate, and the metal from the top or second layer diffuses through the bottom or first layer and effectively alters the gate work function of the second metal gate.
In order to fabricate bulk p- and n-MOS devices with favorable threshold voltages, one of the metals must have a work function similar to that of n-type silicon (for example, Ti, Ta, Nb), and the other metal must have a work function similar to that of P-type silicon (for example, Ni, Ir, Mo). It is also important that the second metal (top layer metal) has a sufficiently high diffusivity in the first metal (bottom layer metal) and has a propensity to segregate to the gate dielectric interface. A good example of such a pair of metals is Ni and Ti. Ni diffuses easily through Ti and segregates at the silicon oxide interface.
In other embodiments, a barrier layer can be provided between the first and second metal layers over the doped well where no metal diffusion is desired. This is done before the second or top metal layer is formed by first forming the barrier layer over both wells and then selectively removing the barrier layer where metal diffusion is desired. Alternatively, the barrier layer can be left in place over both wells, and after the second metal layer is formed over the barrier layer, the barrier can be effectively removed from over one well by selective ion implant into the barrier layer.
The metal diffusion process is readily employed either before or after source and drain formation, thereby avoiding high temperature processing in forming the source and drain regions, if necessary.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.